Several system on a chip (SoC) devices implement the Cortex-A9 core, including:
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Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution.ĪRM states that the TSMC 40G hard macro implementation typically operates at 2 GHz a single core (excluding caches) occupies less than 1.5 mm 2 when designed in a TSMC 65 nanometer (nm) generic process and can be clocked at speeds over 1 GHz, consuming less than 250 mW per core. Jazelle DBX support for Java execution. Thumb-2 instruction set encoding reduces the size of programs with little impact on performance. 
High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional). NEON SIMD instruction set extension performing up to 16 operations per instruction (optional). Out-of-order speculative issue superscalar execution 8-stage pipeline giving 2.50 DMIPS/MHz/core. Main article: Comparison of ARMv7-A cores
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